The present invention relates to a phase synchronizing circuit for generating a clock which is synchronized with, and follows up the phase of, an input signal, and more particularly, to a phase synchronizing circuit exhibiting an excellent phase synchronizing characteristic and capable of being applied to zone bit recording for use in a hard disc system or the like.
Hitherto, the structure of a phase synchronizing circuit widely used in a data separator or a frequency multiplexing circuit of a magnetic disc apparatus has been arranged as shown in FIG. 7 to include a phase comparator 10 for performing a comparison between the phase of an input signal S.sub.IN, which is a reference signal, and that of an oscillator output signal V.sub.OUT, at the oscillator frequency f.sub.osc from, a voltage controlled oscillator 40 so as to output a delayed phase difference detection signal Q.sub.1 and a leading phase difference detection signal Q.sub.2, and a charge pump 20 for supplying charging/discharging electric currents to a capacitor C.sub.F of an RC loop filter 30 in accordance with the delayed phase difference detection signal Q.sub.1 and the leading phase difference detection signal Q.sub.2. The loop filter 30 which is a low-pass filter (LPF) constitutes a lag lead filter which provides a filter output voltage V.sub.F which controls the frequency f.sub.osc of the oscillator output voltage V.sub.OUT, which corresponds to the value of the above-described input. The voltage controlled oscillator 40 is constituted by a voltage-current converting circuit (hereinafter called a "V/I converting circuit) 42 and a current-frequency converting circuit (hereinafter called an"I/F converting circuit) 44. The oscillating frequency f.sub.osc of the voltage controlled oscillator 40 may be supplied to the phase comparator 10 via a predetermined divider.
The phase comparator 10 is a digital phase comparator which is constituted by, for example, a pair of D flip-flops and a logic gate. The charge pump 20 is, as shown in FIG. 8, a series circuit constituted by an insulating-gate field effect transistor (hereinafter called a "MOSFET") 22 which is turned on to supply a charging current i.sub.1 in response to a low level value of the delayed phase difference detection signal Q.sub.1, a charging electric current source 24, a MOSFET 26 which is turned on to supply a discharging current i.sub.2 in response to a high level value of the leading phase difference detection signal Q.sub.2, and a discharging electric current source 28.
As shown in FIG. 9, the charging fixed electric current source 24 and the discharging fixed electric current source 28 are respectively constituted by current mirror circuits. The value of the charging electric current and that of the discharging current are both equal to the value of a mirror electric current i.sub.1 which is determined in accordance with the value of a charging/discharging electric current value setting resistor Rx.
FIG. 10 illustrates an embodiment of V/I converting circuit 42. This circuit is constituted by a voltage-electric current converting portion 42a for varying the value of an electric current i.sub.3 in accordance with the value of the filter output voltage V.sub.F and a current mirror circuit 42b for deriving an output electric current i.sub.3 from input electric current i.sub.3. The converted electric current i.sub.3 in the voltage-electric current converting portion 42a of V/I converting circuit 42 is represented by the following equation: EQU i.sub.3 =(V.sub.DD -V.sub.F)/R.sub.Y ( 1)
where R.sub.Y is a converted electric current value setting resistance of an op-amp OP in portion 42a and V.sub.DD is the power supply voltage for circuit 42.
However, a phase synchronizing circuit constituted as described above is associated with the following problems:
(1) When the phase synchronizing circuit is constituted by a semiconductor integrated circuit, the characteristics of the transistors which constitute the phase synchronizing circuit exhibit substantial differences from one another due to the manufacturing process. Therefore, the current-frequency conversion coefficient k of I/F converting circuit 44 inevitably has a different value in each product. That is, if the I/F converting circuits 44 of two phase synchronizing circuits have respective conversion coefficients k and k+.delta.k, they receive respective electric currents i.sub.3 and i.sub.3 +.delta.i.sub.3 when the input signal S.sub.IN and the oscillator frequency f.sub.osc of VCO 40 are synchronized with each other. However, since the charge pump 20 charges/discharges the loop filter 30 with the fixed electric currents supplied from the fixed electric current sources 24 and 26, the closed loop gain G of the phase synchronizing circuit inevitably varies considerably between products. The variations in gain G will cause corresponding variations in the specific frequency .omega..sub.n and in the damping factor .zeta. which characterize the phase synchronizing circuit. Consequently, the yield of the semiconductor phase synchronizing circuits deteriorates.
(2) On the other hand, the electric elements of the circuits are arranged to have the most suitable values in order to synchronize the phase with the input signal S.sub.IN at a special frequency. For example, the value of the charging/discharging electric current i.sub.1 of the charge pump 20, the time constant of the loop filter 30 and the I/F characteristic are determined in the above-described manner. When the frequency of the input signal S.sub.IN is switched to a different value, also the frequency component such as the jitter is changed. As a result, it is necessary to perform an adjustment to again give each of the parameters of the above-described circuit elements the most suitable value.
Specifically, in a case where clocks having different frequencies are applied as the input signal after they have been switched, it is necessary to preliminarily provide a plurality of loop filters having different time constants to switch to the most suitable loop filter so as to synchronize with the frequency switching. That is, input signals having different frequencies must be received by the corresponding loop filters provided. For example, in a case where zone bit recording is realized in a hard disc system, a plurality of loop filters must be used, causing the structure of the phase synchronizing circuit to be unduly complicated. Therefore, calculations must be performed to give the circuit constant the most suitable value for each of the frequencies of the input signals.